Many reduced instruction set computer (RISC) processors known in the open art are based on the pipeline principle, wherein the function of the processor is divided into certain basic phases, or units. Pipelining techniques are especially well known in digital signal processor (DSP) technology. A pipeline processor enhances execution speed by separating the instruction processing function into at least three pipeline phases. This phase division allows an instruction to be fetched, while a previous instruction is decoded, and an instruction before that is executed. Each phase of the pipeline normally requires one process cycle to complete, such that the total elapsed time to process (i.e., fetch, decode and execute) a single instruction is three machine cycles. However, the average throughput is one instruction per machine cycle because of the concurrent nature of operations of the three pipelined phases.
Once a pipeline is full, processor performance is limited by the phase which requires the longest to complete. In pipeline processing, this is usually the execute phase. Accordingly, the processor normally has excess time in both the fetch phase and the decode phase. The present invention attempts to maximize utilization of all processor phases.
Previous attempts have been made in the art to improve RISC-type processor performance. One approach has been to change the technology used in implementing the processor, so that the processor operates at a higher clock frequency. However, changing from established technology can entail substantial risks, and consume substantial time and resources by requiring adaption of existing architecture to new technology. In addition, even after converting to a new technology, the faster processor phases will still have excess, unused time.
Another known technique to increasing processor speed is to enhance the processor's instruction set with faster instructions. However, adding faster instructions requires the coding of software to utilize these instructions. If a large software application base already exists for the processor, then it is unlikely that the software will be recoded to use the new, faster instructions because of the time and expense which would be involved. In addition, such changes often make the software programs incompatible with older machines. In any event, this approach does not solve the intrinsic problem of the pipelined processor having excess, unused time in the faster phases.
Therefore a new RISC-type, pipelined processor which increases instruction throughput without changing technology or requiring a more complex instruction set, yet maximizes utilization of all processor phases, is needed in the art. The present invention provides such a processor and its associated processing methods.